LVDS Receiver PLL

Hello once again,

scanning the documentation for the keyword "same i/o standard", I finally could find a sentence mentioning the said restriction under PLL Clock Feedback Modes. For Zero Delay and External Feedback Mode a restriction applies:

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Altera requires that you use the same I/O standard on the input clock, and output clocks.

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The point is, if I understand right, that using the same I/O standard is necessary to achieve a specified PLL timing relationship. In my example, however, he PLL is using normal feedback mode. For this mode, no restriction regarding I/O standards is written in the manual. Using DPA to achieve source synchronous LVDS receiver timing, this seems reasonable.

Additionally, the restrictions, as far as they really exist, should be listed in the PLL Pin overview and in the Clocking and I/O-Standards chapters.

Regards,

Frank