Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorLVDS problem on the De2-70
I use de2-70 board to test the LVDS voltage values. My design is posted below. Now I got a odd problem. The signal derectly outputed by PLL, its average voltage is 1.2V and maximum voltage is ...
Altera_ForumHonored Contributor
Honored ContributorSeems like you never consulted the Cyclone II LVDS specification. Unlike Cyclone III or high end FPGA, Cyclone II doesn't provide a true LVDS driver. It needs external resistors, either in the 3R (Device Handbook Figure 11-3) or the 1R/RSDS configuration (Figure 11-7). In addition, a 100 ohm differential load at the receiver must be present to get the correct LVDS level.
The DE2-70 board isn't actually wired for differential signaling. You have additional 47 ohm series resistors in the input protection network that must be taken into consideration.
