LVDS Links bet. Cyclone and Cyclone III

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When a LVDS receiver is operated source-synchronous with an external supplied clock, the receiver PLL must be driven from this clock. Sharing the PLL means clocking the transmitter from the external clock, too. This can work only at one side of the link and involves additional jitter for the TX clock and data, which is most likely unwanted.

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Thanks a lot.

LVDS receiver must operated in source-synchronous mode, unless soft CDR mode is supported by the device, isn't it?