LVDS Links bet. Cyclone and Cyclone III

Using non-dedicated pins for clock output introduces additional skew and some jitter. In most cases, it should be acceptable.

When a LVDS receiver is operated source-synchronous with an external supplied clock, the receiver PLL must be driven from this clock. Sharing the PLL means clocking the transmitter from the external clock, too. This can work only at one side of the link and involves additional jitter for the TX clock and data, which is most likely unwanted.