LVDS clock and data signals, interfacing to LVDS DAC

Hi Rysc,

I am reading throught the time quest guides and I have figured something out. Basically it seems like my design cannot respect the time constraints when handling the 737.28 MHz PLL output.

I have been able to write my sdc file, correcting the constraints for some other signals inside my circuit, but i still see not effect on this clock output. Time quest is showing me always a negative slack value for this signal, and I cannot manage to get it better.

The only thing I could try was compiling the project, optimizing it for speed, in this way I have reached a 10 percent more for the slack variable, but it is still negative (-0.600).

Now my questions are the following, according to my small experience:

1) Can the ALTPLL Megacore handle my 737.28 MHz clock signal?

2) Of course I get even warnings about the fact the the PLL megacore function outputs are feeding non dedicated clock pins, and this is effecting on the jitter, so the time performances are degradated....On the time quest analyzer I see that for the PLL output c0 there is a maximum frequency of about 460 MHz.....The pins I am actually feeding are just clock output pins on a specific HSMC connector on my development board. Let´s assume that I cannot drive those pins correctly with the ALTPLL megacore, the warning says that in zero-delay buffer mode the jitter could be compensated. Now I don´t know how this exactly works, I have read a short explanation on the guide but an example could be much more illuminating for me. Is there a source where I can see how I can use this PLL configuration? I have seen that two new pins are added (fbin, fbout) to the block but I don´t know how I should connect them.

3) About the usage of LVDS dedicated megacore functions, I see difficult to reach my interleaving in that way. Let´s say I transmitt 32 bits and I apply a serialization factor of 2, I then have my interleaved data in output, but an output data clock which is the half of the original. If I would like to go for this implementation I suppose I should double the data rate before this block, in order to get the interleaved data with the right frequency, but then I would have to manage 1.5 GHz, which I suppose it´s not internally reachable.

Just in order to give you an overview of my design, I attach here the data format to be delivered to my DAC board, and a schematic of my design.