LVDS clock and data signals, interfacing to LVDS DAC

You need to separate the IO standard from the logic behind it. (Altera doesn't do a good job of this in its naming).

- If you make an LVDS IO standard assignment, then you only need the P pin. If you look in the fitter report, Input/Output Pins section, you should see they have the correct I/O standard and you should see an n pin has been created. Naturally, make sure it's hooked up where you want.

- Inside the FPGA, you can use DDR I/O, but you will need to enter timing constraints. I wrote a source-synchronous timing constraint document on alterawiki:

http://www.alterawiki.com/wiki/source_synchronous_analysis_with_timequest

It's long, but there are some examples you can probably cut and paste from.

- Is the data rate 737Mbps, i.e. the same as the clock? I only ask because most interfaces usually have the clock run at half the data rate(which is where DDIO functionally works). Assuming it is 737Mbps, it is going to be difficult to meet timing with DDR I/O. Stratix IV has dedicated LVDS hardware, which can be instantiated with the altlvds_rx and altlvds_tx megafunctions. It runs really fast, so I would suggest using that. It's timing analysis is also greatly simplified. You don't create timing constraints, and instead run Report TCCS and Report RSKM in TimeQuest. It's actually too simplified, i.e. Report TCCS will just say 100ps, i.e. there's 100ps of channel-to-channel skew, but it won't even say what pins it's talking about, and it won't say the clock/data relationship, i.e. if it's center-aligned or edge-aligned, so you need to be sure to set that up correctly in the megafunction.