LVDS and Cyclone II Nios DEV Kit

FvM,

Thank you very much for the response. I've got more additional questions very important for me.

I have a core, this is a master of a 4-bit wide bus ( Pclk, synch, TX, RX).

PCLK is 8MHz. I want to use Cyclone II I/O LVDS differential mode for them. Is it just enough to set LVDS standard in the appropriate column of the Pin Planner or I should use special primitives?

Is there some application notes with examples how to use LVDS signalling with ALtera FPGA.

And the second question, what blocks can I use if TX should be tri-stated? It’s used to allow the transmission of data by multiple sources in adjacent timeslots without the risk of driver contention.

Thank you.