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Altera_Forum
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17 years ago

LVDS (2.5V) in Banks where JTAG and Config Pins reside?

Hello, I want to use the Bank 2, 5 and 6 of the Cyclone II EP2C35F484 for LVDS communication. An FAE from Sasco Holz (Arrow) told me, that i should use the left and right banks for LVDS instea...
Altera_Forum's avatar
Altera_Forum
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16 years ago

The problem is, that LVDS driver as well as receiver behaviour for 3.3V VCCIO is completely unspecfied. If it works in your design, possibly with an non-LVDS compliant VCM level, you can't be sure, if it's only working by chance. I would expect, that it's O.K. for reduced speed requirements, but it's more or less guessing.

It's much easier to operate the JTAG interface with VCCIO of 2.5V, all JTAG inputs can be interfaced with a 3.3V JTAG chain, only TDO may need a buffer for level translating, but only, if the next device in the chain can't work with 2.5V input level as well.