Altera_ForumHonored Contributor16 years agoLUTs vs Logic Elements/Cells Hi, I am currently doing initial analysis on a design. I am researching different FPGA´s regarding the required resources to implement different features. I cannot find a method of relatin...Show More
Altera_ForumHonored Contributor16 years agoin a Stratix III/IV, half the LABs are MLABs which are a little bit like distributed RAM.
Recent DiscussionsPower-Down Sequence Requirements for the Agilex 7 F-Series(2x F-Tile) DevicesRegarding Power-Up Sequence for Agilex 5Cyclone V SoC 5CSXC6 Series GXB Utilization and LimitationsHow to tell Quartus my Arria10 target system CLKUSR frequency is 100MHz?Agilex 3 PLL in Source Synchronous mode ?