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Honored Contributor
Honored Contributorlpm_fifo error
Fifo specification lpm_dcfifo showahead 8 bit in 32 bit out 8bit x 2048 Size 40 Mhz writeclk 85 Mhz readclk Fifo created with megawizard Quartus 7.2sp3 underflow and overflow pr...
Altera_ForumHonored Contributor
Honored ContributorCould you correlate the last statement(about the write pointer ticking) with the previous statement(that the read counter flips and reads back to 0)? I'm sure they're related, just not sure how you're seeing them.
Can you attach the Megafunction? I doubt it will show anything, but just a thought. As a note, the asynchronous FIFO is probably used in 90% of Altera FPGA designs, since everyone has to handle transfering data between asynchronous clocks, so I have a lot of confidence in the core. (I'm just throwing that out there in case you're concerned that it's something intrinsic to the FIFO.) If you can grab all the flags, as well as a lot of the internal registers to the FIFO in SignalTap at the time of the failure, something might show up.
