Low Pass IIR filter using cyclone II FPGA

Hello people,

I saw mult_accum.pdf file you suggested me. Ok, there is some Wizard which guide me through the process of creating multiplier. Is there any chance to see the VHDL code of that multiplier created by the wizard?

I didn't see that multiplier can perform multiplication with fixed point unsigned numbers.

Please advice,

Regards,

Bojan

1 . If your N bits ADC is not two's complement:

add to the conversion result 2^(N-1) in order to convert to signed.

2. multiply de x(n-i) sample with filter coefficient, result will be : N + N_coeff

the simplest way to round is with an N_frac bits rigth arithmetic shifting. N_frac es the fractional part length.

Hello people...

In attachment I gave you block diagram of my filter design.

And I want to ask you something...

I will multiply my 18bits sampled input signal with 18bits fixed point coefficient (6.12). [x(n)*a]. Result will be 36bits wide, and 12 LSBs of the result are fractional part, right. Can I exclude these 12 fractional bits from further calculation?

If my output from FPGA must be 18bits wide how to threat 24 bits of multiplication result? I pick up just 18 LSBs?

If I get at least one 1s on 6 MSB positions of 24 bit multiplication result I should pick up 111111111111111111 for the result, right?

Please advise me If my way of thinking is all right?

Thank you in advance!

Bojan

Hi Bojan.

First of all let's suppose that your multiplier has an unsigned result.

Everything that you want to implement into your FPGA can be simulated in Matlab before. The final goal is to exploit the full 18bits dynamic range of your final DAC.

So you have to analyze the output of your multiplier and see what dynamic range has its output (this will depend on the filter input and on the coefficients). The 18 bits that you have to send to your DAC (supposing that the DAC accepts unsigned inputs) are the first MSBs starting from the highest bit that shows a variation at the multiplier output. In this way your DAC output will be maximized.

Once you have simulated everything in Matlab you can design your truncation block at the multiplier output.

Hi,

Is it better for me to choose AD converter which gives a signed 2's complement result of coversion?

Bojan

--- Quote Start ---

So you have to analyze the output of your multiplier and see what dynamic range has its output (this will depend on the filter input and on the coefficients).

--- Quote End ---

I expect, that the filter should have a defined nominal gain rather than determining the gain empirically. That's also the concept behind using fractional number formats to my opinion: Having a defined filter function and choosing a signal and coefficient scaling

from known signal characteristics. If filter blocks with a gain different from unity are cascaded, there is a danger of over- or underflow. It should be checked either with typical signals in a hand calculations or at best in a fixed point simulation.

--- Quote Start ---

If my output from FPGA must be 18bits wide how to threat 24 bits of multiplication result? I pick up just 18 LSBs?

--- Quote End ---

Using a fixed 6.12 scaling through the signal chain means discarding 6 high and 12 low bits after each multiplier. For the discarded high bits, a saturation logic should be used, including correct sign handling of course.

Two additional points: A resolution of 12 fractional bits may be too low for the low frequency end of filter characteristics. It may also result in inacceptable high quantization noise at low input levels.

Folks,

One question is bothering me this time...:confused: concerning LowPass filtet of course.

I have input signal range within, let's say, x(t)[-5,5V], and I've designed filter transfer function with some coefficients. I sample x(t) in a specified moment of time and I perform filter calculations using that sample and a some previous samples.

Does it means that each calculated output y(t) must be within a range of my input signal x(t) or not?