Low Pass IIR filter using cyclone II FPGA

Hi Bojan.

First of all let's suppose that your multiplier has an unsigned result.

Everything that you want to implement into your FPGA can be simulated in Matlab before. The final goal is to exploit the full 18bits dynamic range of your final DAC.

So you have to analyze the output of your multiplier and see what dynamic range has its output (this will depend on the filter input and on the coefficients). The 18 bits that you have to send to your DAC (supposing that the DAC accepts unsigned inputs) are the first MSBs starting from the highest bit that shows a variation at the multiplier output. In this way your DAC output will be maximized.

Once you have simulated everything in Matlab you can design your truncation block at the multiplier output.