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Altera_Forum
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17 years ago

Low Pass IIR filter using cyclone II FPGA

Hi everyone, I hava a task to implement low pass iir filter on cyclone II FPGA. The parameters of filter are the following: fp=5kHz; pass band frequency fs=8kHz; stop band frequency Fs=44k...
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Altera_Forum
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17 years ago

Hello people...

In attachment I gave you block diagram of my filter design.

And I want to ask you something...

I will multiply my 18bits sampled input signal with 18bits fixed point coefficient (6.12). [x(n)*a]. Result will be 36bits wide, and 12 LSBs of the result are fractional part, right. Can I exclude these 12 fractional bits from further calculation?

If my output from FPGA must be 18bits wide how to threat 24 bits of multiplication result? I pick up just 18 LSBs?

If I get at least one 1s on 6 MSB positions of 24 bit multiplication result I should pick up 111111111111111111 for the result, right?

Please advise me If my way of thinking is all right?

Thank you in advance!

Bojan