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So you have to analyze the output of your multiplier and see what dynamic range has its output (this will depend on the filter input and on the coefficients).
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I expect, that the filter should have a defined nominal gain rather than determining the gain empirically. That's also the concept behind using fractional number formats to my opinion: Having a defined filter function and choosing a signal and coefficient scaling
from known signal characteristics. If filter blocks with a gain different from unity are cascaded, there is a danger of over- or underflow. It should be checked either with typical signals in a hand calculations or at best in a fixed point simulation.
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If my output from FPGA must be 18bits wide how to threat 24 bits of multiplication result? I pick up just 18 LSBs?
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Using a fixed 6.12 scaling through the signal chain means discarding 6 high and 12 low bits after each multiplier. For the discarded high bits, a saturation logic should be used, including correct sign handling of course.
Two additional points: A resolution of 12 fractional bits may be too low for the low frequency end of filter characteristics. It may also result in inacceptable high quantization noise at low input levels.
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