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AGaru1's avatar
AGaru1
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6 years ago

Low Latency 100G Ethernet Intel FPGA IP Hardware Design Example

Hi everyone,

I want to create a loop between 2x Low Latency 100G Ethernet Intel FPGA IP Hardware Design Example on a Stratix 10 MX. The main idea is to implement the entire example design described in alt_e100s10.v twice inside a top level module. The only doubt is given by the avalon jtag master bridge. Can i instantiate two of them, one for each instance? And if not, can i use the Ethernet Link Inspector for the two different instances with only 1 avalon jtag master bridge?

If i was not clear enough, please ask me questions.

Thank you.

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  • AGaru1's avatar
    AGaru1
    Icon for Occasional Contributor rankOccasional Contributor
    5 years ago

    Hi,

    i temporarely stopped working on transceivers. Now i'm back on it and i'm trying to figure out the pinout. I downloaded the 1SM21C document by Intel.

    I don't understand the relation between the pins and the transceivers. For example, the board i'm using is a BittWare 520N-MX with an Intel Stratix-10 FPGA connected to four QSFP28 ports.

    I need to use two of those QSFP28 ports. In particular i need to use the Ethernet 100Gb Hard IP which seems to be usable via port 2 and 3 on the board. So i'm looking forward to the pinout of the port 2 and 3.

    The board document says that:

    QSFP0_RX[0]p -> pin BB45

    QSFP0_RX[0]n -> pin BB44

    QSFP0_TX[0]p -> pin BD49

    QSFP0_TX[0]n -> pin BD48

    and then it says that the rest of the pin mappings follow numerically.

    Then i took a look at the Intel document 1SM21C.

    I'm a bit confused because in the verilog code RX and TX wires are buses [3:0] so each of them is made of 4 wires.

    I don't understand what pin corresponds to each of those wires and also how do i differentiate each QSFP(n) from each other.

    For example, i want to use QSFP2 and QSFP3 and i know that each rx and tx wires are composed of 4 wires each. How should i look at the Intel document?

    Sorry i'm new to it ...

  • AGaru1's avatar
    AGaru1
    Icon for Occasional Contributor rankOccasional Contributor
    5 years ago

    Hi i have another question. I made a wrapper with 2 instances of the IP. It gets synthetized and implemented correctly but it doesn't pass the timing analysis (there is an epic slack, like -90). I don't understand why, i'm looking the paths and it seems like it's something related to the pll that generates the clk100. Have you got any advice please?