Loss of lock in the PLL of ALTLVDS_Rx

Creating ALTLVDS_Rx with external PLL is time-taking procedure for my project (it is necessary to rewrite several finite state machines related to ALTLVDS_Rx). I'll do it during some days.

And I have one more idea about PLL of ALTLVDS_Tx. After compilation there is critical warning: PLL"altlvds_tx0:inst23|altlvds_tx:altlvds_tx_component|lvds_tx_7ki1:auto_generated|lvds_tx_pll" input clock inclk[0] is not fully compensated because it is fed by a remote clock pin "Pin_90".

To compensate tx_inclock of ALTLVDS_Tx I have decided to cascade main PLL of my project and PLL of ALTLVDS_Tx. Namely, I created one more clock output "clk_lvds" (20 MHz) in main PLL and reconfigured main PLL in source-syncronous mode with compensated clock "clk_lvds". This new clock "clk_lvds" feeds input "tx_inclock" in ALTLVDS_Tx.

After compilation the warning appeared:

PLL"altlvds_tx0:inst23|altlvds_tx:altlvds_tx_component|lvds_tx_7ki1:auto_generated|lvds_tx_pll" input clock inclk[0] is not fully compensated and may have reduced jitter performance because it is fed by a non-dedicated input.

And attached to warning info message:

Input port INCLK[0] of node "altlvds_tx0:inst23|altlvds_tx:altlvds_tx_component|lvds_tx_7ki1:auto_generated|lvds_tx_pll" is driven by altpll0:inst38|altpll:altpll_component|altpll_67s2:auto_generated|clk[3]~clkctrl which is OUTCLK output port of Clock control block type node altpll0:inst38|altpll:altpll_component|altpll_67s2:auto_generated|clk[3]~clkctrl.

I see, there is no cascading of PLLs. How can I do it?

Thanks.

Instead of cascading of PLLs, I changed clock generator. Now it is Jauch O 10,0-JO75-B-3,3-2-T1-LF. Its phase jitter < 1 ps and frequency stability is 50 ppm. Previous generator (Golledge, GXO-7531) had 50 ppm and its phase jitter was unknown, I think it was very bad as manufacturer didn't publish it.

After continuous hard test (during 3 days) it was only one loss of lock !!!

It is amazing result.