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Honored Contributor
Honored ContributorLoss of FPGA configuration
To minimize power consumption, I have the Oscillator input of the main part of my Stratix III design gated (glitchfree keeping low, if gated). Connected to this clock (50 MHz) are two synchron...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- However: I still observe significant power supply dip on VCCL(1.1V) and VCCPD (2.5V) when activating the reset (without clock gating), and I assume the POR did just not trigger (but may do so on another device...). Maybe I have some illegal bank voltage combination (did check that, but found no offending conditions so far)? --- Quote End --- The observation seems to suggest, that the suspected power supply drop below reset threshold happens at internal nodes (PLL and core supply) and not peripheral supply, as I previously guessed. This changes the picture. I wonder, if the current transient may be normal operation and the voltage drop primarly a board hardware problem. To get clarity about the effect, I would either measure the respective supply rail dynamic current or check the power supply transient response with a test load.
