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Honored Contributor
Honored ContributorLoss of FPGA configuration
To minimize power consumption, I have the Oscillator input of the main part of my Stratix III design gated (glitchfree keeping low, if gated). Connected to this clock (50 MHz) are two synchron...
Altera_ForumHonored Contributor
Honored ContributorHi:
The Loss of configuration should only happen at Power on Reset, or by pulling nCONFIG low. The Supply's associated with the Power on Reset are VCCPT, VCCPGM, VCCPD VCC and VCCL as shown in Figure 10-3 in the handbook. but other supplies VCCA_PLL VCCD_PLL VCCIO and VCC_CLKIN are also mention in the tRAMP Requirements in Table 10-1. (See Handbook pages 10-4 and 10-5) Another possible issue would be with the nCONFIG pullup is weak, or has a short to your clock enable signal in the bad case. A third Possibility is that instead of the PLL settling to zero, it runs wild. And actually draws more current than your expecting, causing one of the supplies to droop. You may want to either pull all power from the FPGA if you can to save maximum power, or clock gate internally in the FPGA after the PLL.
