Hello, I want to implement sine and cosine signals in vhdl to check a part of my code but i don't know how to initialize these sin and cos signals? please tell me what is the way to do it? i have read that it is possible through LUT but i don't know what LUT is ???

A lut is a ROM containing all of the Sin Values - so for a table of sin(x) - x is the address to the ROM.

Hi! I have the same project.I want to create sin-signal for tests, but it's an error when I put negative numbers into .mif file. Insted of negative numbers Questa show me zeros. How Can I solve this problem? Main code: module single_rom ( addr, clk, q ); //input input addr ; input clk; output signed q; //ip-cores rom_ip rom_ip_component ( .address (addr), .clock (clk), .q (q)); endmodule Testbench: `timescale 1 ps/ 1 ps module single_rom_tb(); // test vector input registers reg addr; reg clk; // wires wire signed q; // assign statements (if any) single_rom i1 ( // port map - connection between master ports and signals/registers .addr(addr), .clk(clk), .q(q) ); //clk initial begin clk = 0; forever# 10 clk = ~clk; end //beginning address initial addr = 7'h00; //loop always begin @(posedge clk) if (addr >= 7'h64) addr = 7'h0; else addr = addr + 7'h1; end endmodule Contents of .mif file: WIDTH=16; DEPTH=110; ADDRESS_RADIX=UNS; DATA_RADIX=DEC; CONTENT BEGIN 0 : 0; 1 : 5; 2 : 15; 3 : 80; 4 : 345; 5 : 656; 6 : -1; 7 : -2; 8 : -3; 9 : -4; 10 : -5; 11 : -6; 12 : 20886; 13 : 22430; 14 : 23885; 15 : 25247; 16 : 26508; 17 : 27665; 18 : 28713; 19 : 29648; 20 : 30465; etc Picture, you can see zeros instead of negative numbers: http://s7.hostingkartinok.com/uploads/thumbs/2014/11/03327b0a1b3e6e4dc3e1dd541e47935d.png (http://hostingkartinok.com/show-image.php?id=03327b0a1b3e6e4dc3e1dd541e47935d)

I don't about your tools habits but you can convert negative numbers to positive (bit equivalent): e.g. for n bits negative values (signed) data = data + 2^n

--- Quote Start --- I don't about your tools habits but you can convert negative numbers to positive (bit equivalent): e.g. for n bits negative values (signed) data = data + 2^n --- Quote End --- Thank's for your answer, but I did it and I got the following picture it Questa. I can't submit it like a signed number. In radix I use decimal, but it also ansigned. How can i transform it into unsigned? http://s7.hostingkartinok.com/uploads/images/2014/11/504de2f5c58eae37f09eb5c10191f761.png (http://hostingkartinok.com/show-image.php?id=504de2f5c58eae37f09eb5c10191f761)

Not sure if this will fix your problem, but try replacing the "signed" declarations with "integer" in your main code and testbench.

LookUp Tables | Altera Community

12 Replies

Altera_Forum
Honored Contributor
11 years ago
The wave screenshot posted above already shows a different problem than what you have reported initially. The negative values are not replaced with zeros anymore, rather you seem to be missing the sign bit this time. You need to inspect the values shown in the diagram to be able to tell what's happening - for example, what is the value at the peak of the sinusoid? For 16bit signed integer, your values in the LUT/MIF should be in the [-32768;+32767] interval, are they?
Altera_Forum
Honored Contributor
11 years ago
--- Quote Start ---
I did it, but it didn't fix my problem.

--- Quote End ---

your mif file is set to unsigned radix but the data ia signed so keep it signed and change radix in mif file to signed

Forum Discussion

LookUp Tables

12 Replies

Recent Discussions

Marking codes of CY10CL040YF484

Unable to scan JTAG chain, TCK only 2V

Cyclone 10 LP Bitstream Compression Failing

Updated .brd file for Stratix 10 GX dev kit

Agilex 5 D-Series HVIO IOPLL runtime reconfiguration: C0 write succeeds, but output remains 100 MHz