Looking for FPGA that can have FF and shift register that can clock at 1GHz

Although FPGA's have improved greatly since 2005, 1 GHz is still pushing the edge.

Is the data coming in on SERDIES?

Right now Stratix V PLL VCO frequency maxes out at 1.6 GHz. So 800 MHz is the max showing up in the datasheet for output clock of the PLL, (although the PLL mega wizard is letting me generate a 1 GHz clock using the integer PLL.

But getting it to do much of any logic at that speed will be very difficult to say the least.

Pete

As far as I know all FPGAs top out in the hundreds of MHZ range (except for serial transceivers). Some have Arm processors integrated. Some of these can operate with an internal clock at 1 GHZ.

The fastest (and most expensive) families are the Stratix from Altera and the Virtex from Xilinix.

The latest Quartus version is 15.0. There is a free version of modelsim available, but it runs slowly and can't handle large designs.

Looking at the upcoming Arria-10 switching characteristics.

Maximum clock speed is 644MHz.

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Although FPGA's have improved greatly since 2005, 1 GHz is still pushing the edge.

Is the data coming in on SERDIES?

Right now Stratix V PLL VCO frequency maxes out at 1.6 GHz. So 800 MHz is the max showing up in the datasheet for output clock of the PLL, (although the PLL mega wizard is letting me generate a 1 GHz clock using the integer PLL.

But getting it to do much of any logic at that speed will be very difficult to say the least.

Pete

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Thanks for the answer.

The 1GHz clock can be internal, it's not being fed externally. Also the output is much slower.

Basically, I have external circuit that trigger the FPGA, inside the FPGA, I need to synchronize the random trigger with the internal 1GHz clock. Then I am going to Demux it down to a slower clock speed.

If I can have 10 of the 8bits register that run at 1GHz, I can have a way to demux to a wider data at slower speed for processing.

Do you think Xilinx has faster FPGA that can run at 1GHz? Or it's just more of the same?

Thanks

Alan

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The 1GHz clock can be internal, it's not being fed externally. Also the output is much slower.

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What is so special about running your internal logic at 1GHz?

Most practical systems that need to process digital data at a higher rate than the FPGA fabric can handle just process it in parallel, or as you refer to it, demux the data.

I have designs that interface to 1GHz ADCs and process data at 125MHz, and other designs that interface to 20GHz ADCs and process data at ~200MHz.

For practical FPGA designs (you try to fill up your expensive high-density FPGA), anything approaching 300MHz will start to get tricky to meet timing, and the FPGA will start to get hot :)

Cheers,

Dave

As you notice by now, I am not a FPGA designer. Just an RF analog engineer contracted to company called Revera. I did design FPGA using Apex 10 years ago and was a success. I just learn what it takes to do the job and no more. I need to find the fastest FPGA to do the job, with minimal amount of "tricks" in design to get the job done. So I am willing to pay for a FPGA that is way over kill for this simple but fast task. It is not an issue to get a big one that I use only 10% as long as it has enough clock structure to support the task.

This is really a simple 16 channels event counter with coincident detector. But I need to detect if two channels receive trigger within 1nS and considers as being a single event that trigger both channels. If it is determined the trigger of the channels to be coincident, then I need to count as one event even though more than one channel receives a trigger.

So I need to sample 16 separate channels input at 1GHz as I need to determine coincidence between the channels. After that, it's just simple to sum the total events within 5uS and be read out.

It is very simple, but as you can see, I need to read all 16 channels at the same time with a 1nS clock. That will be at least one register being clocked at 1Ghz.

After that, I can quickly demux it out to say 8 different 16bit registers to perform coincident screening and add the total counts at 125MHz. BUT those 8 16 bit registers still have to meet the setup and hold time for 1GHz clocking even though it is being clocked at 125MHz.

Also, I need a 5 stage shift register right at the input of each of the 16 channels to generate signal to prevent retriggering and other things. those 5 X16 DFF has to be clocked synchronously at 1GHz before even performing demuxing and adding.

As you can see, the trigger of the 16 channels are coming in externally, the 1GHz clock is generated internal to the FPGA. The total count is being read out and reset the counter upon each reading. Just that simple!!!

Please advice what FPGA can do what I want. I suspect I need a FPGA that have enough registers and FF to do the job and the rest are quite empty!!!

Thanks

The serdes is the non fpga part of fpga!. It is not configurable logic but sometimes can be exploited.

A Serdes channel accepts serial data at high frequencies(Gigas) and internally outputs parallel data to the fpga at slow fabric rate depending on chosen serialisation factor.

Thus you may be able to pass the fast channels and their tigger as serdes channels and see the slow parallel side if of any use in your specific task.

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The serdes is the non fpga part of fpga!. It is not configurable logic but sometimes can be exploited.

A Serdes channel accepts serial data at high frequencies(Gigas) and internally outputs parallel data to the fpga at slow fabric rate depending on chosen serialisation factor.

Thus you may be able to pass the fast channels and their tigger as serdes channels and see the slow parallel side if of any use in your specific task.

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thanks for the reply. can you give me a part number or a family of FPGA so I can read into it?

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As you notice by now, I am not a FPGA designer. Just an RF analog engineer contracted to company called Revera.

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Thanks for describing your background, it makes it easier to help you.

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This is really a simple 16 channels event counter with coincident detector. But I need to detect if two channels receive trigger within 1nS and considers as being a single event that trigger both channels. If it is determined the trigger of the channels to be coincident, then I need to count as one event even though more than one channel receives a trigger.

So I need to sample 16 separate channels input at 1GHz as I need to determine coincidence between the channels. After that, it's just simple to sum the total events within 5uS and be read out.

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What is the signal you are sampling at 1GHz? Is it an analog signal that needs a multi-bit ADC, or is it a signal that can be run through a high-speed comparator, and then that comparator output sampled?

You will face two issues with your external signal; you have to make it compatible with the digital FPGA pins, you have to synchronize it to the FPGA clock domain.

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It is very simple

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No, its not simple. You have 16 different channels in 16 potentially different clock domains that you want to compare ...

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I need to read all 16 channels at the same time with a 1nS clock. That will be at least one register being clocked at 1Ghz.

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But what about metastability? Does it matter if 16 FPGA registers sampling that same signal at 1GHz actually generate a change in logic state 1 clock apart due to metastability?

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After that, I can quickly demux it out to say 8 different 16bit registers to perform coincident screening and add the total counts at 125MHz. BUT those 8 16 bit registers still have to meet the setup and hold time for 1GHz clocking even though it is being clocked at 125MHz.

Also, I need a 5 stage shift register right at the input of each of the 16 channels to generate signal to prevent retriggering and other things. those 5 X16 DFF has to be clocked synchronously at 1GHz before even performing demuxing and adding.

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The trigger filtering can be in the parallel domain, so I don't see this as an issue.

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Please advice what FPGA can do what I want. I suspect I need a FPGA that have enough registers and FF to do the job and the rest are quite empty!!!

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The advice depends on what the external analog signal looks like.

For example, this board ...

https://www.ovro.caltech.edu/~dwh/carma_board/

contains an e2v 8-bit 1GHz ADC. This is what would be needed if your external signal was really "analog" and you had to look for a signal buried in noise, eg., a radar return pulse.

The FPGA on this board is the Stratix II. Altera has Stratix V devices now.

The features you can exploit on the FPGA are; the LVDS receivers operating at 1GHz, or the high-speed SERDES channel receivers operated in lock-to-refclk mode, so that the receivers are synchronously sampling. The SERDES might be a good option if you wanted to oversample the external signal, eg., operate at 4Gbps to sample the signal at 4GHz, and then use logic to detect the pulse and maybe decimate the sample stream. For both of these cases, your external signal needs to be converted to differential format with an amplitude of around 350mVpp to 400mVpp.

You could also use an external high-speed comparator and SERDES. In-Phi used to have a part with a 12Gbps comparator followed by a SERDES.

Cheers,

Dave