How to make many logic locks that are exactly the same as one logic lock?

--- Quote Start --- How to make many logic locks that are exactly the same as one logic lock? --- Quote End --- Hi, do want to duplicate a LogicLock region ????

yes, and how to connect the newly generated ports after duplication?

Should I export a logic lock containging an entity, then import 10 such logic locks, and then how to connect the ports of these 10 entities to other ports?

Hi, you got it half and half... Yes you export/import from lower level to higher level but you connect your ports as usual through your project build-up. The compiler will then know you want the locked module to be there. This is similar to incremental compilation. I personally don't recommend either unless it is very necessary as it has its limitations e.g. yo can't use signaltap (at least as far as I know). kaz

--- Quote Start --- Hi, you got it half and half... Yes you export/import from lower level to higher level but you connect your ports as usual through your project build-up. The compiler will then know you want the locked module to be there. This is similar to incremental compilation. I personally don't recommend either unless it is very necessary as it has its limitations e.g. yo can't use signaltap (at least as far as I know). kaz --- Quote End --- Hi Kaz, I never heard that I can't use signaltap when using incremental compilation. My experience is that it works fine. In order to get the most benefit of incremental Compilation and signaltap you should choose only post-fitted nodes. in this case only the connection to signaltap are new routed. But you can also choose pre-synthesis nodes, but the P&R will take longer, you influence the sythesis and maybe your timing.

Logic lock | Altera Community

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Altera_Forum
Honored Contributor
17 years ago
--- Quote Start ---
how to import one design partition 100 times using tcl script?

Thanks!
--- Quote End ---

Hi sylvest,

do you think you will go with the partiton based flow ? I have to look for a way with a TCL sccript, because I have use the flow actual only with a few, but larger blocks. I don't know how full your FPGA will be with all the multiplier, but at a high uitiliaztion in would be more difficult to find a fit for your design with the hard requirement to preserve the placement and the routing. BTW that is also a advantange of the partition flow, because you can choose between serveral options ( Placement and Routing, Placement, Netlist ).

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Logic lock

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