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Altera_Forum
Honored Contributor
Honored ContributorLock a clock to a 8B10B data stream?
Hi there,
I am trying to find a way to synchronize a chain of equipments but don't want to use a dedicated clock network. If I use the transrecivers in Arria II GX to implement GIGE protocol, can I use the clock recovered from the CDR in receiver channel as the reference clock for the CMU PLL in the transmitter channel? Or, is there a way to lock a local high speed clock to an incoming 8B10B data stream from upstream, and then use this local clock to send out 8B10B data stream to downstream? From the handbook of Arria 2 GX it seems that the recovered clock (from Rx CDR) is not accessible for FPGA fabric or CMU PLLs. Am I understanding this correct? Any comment would be greatly appreciated! Thanks, Hua11 Replies
Altera_ForumAs far as I understand, is rx_clkout the slow clock from receiver CDR PLL. But it's not accessible when using the rate matcher. This restriction is common to all Altera GX receiver designs due to the internal clock architecture.
Apart from the question, if the CDR clock output is accessible, I doubt, if it's suited as a TX reference clock by it's jitter specification.
