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ArthurDent's avatar
ArthurDent
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4 years ago
Solved

Linear phase detector implementation for clock and data recovery in FPGA

Hi I am working on a clock-data recovery (CDR) design where the input data stream is 60Mbps (8B10B encoded). Currently I have a working CDR design which uses a binary phase detector (aka. Alexand...
  • ArthurDent's avatar
    ArthurDent
    4 years ago

    I have decided to drop the FPGA implementation of the CDR, and will look for an external solution.

SyafieqS's avatar
SyafieqS
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4 years ago

Hi Vidar,


Any update on this?


ArthurDent's avatar
ArthurDent
Icon for New Contributor rankNew Contributor
4 years ago

I have decided to drop the FPGA implementation of the CDR, and will look for an external solution.