LED toggle

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I'm trying what I thought would be a very simple programme to turn alternate LEDs ON and OFF every half second, but it isn't working as it should. It starts off OK, with the LEDs toggling about every half a second, but the period soon increases, so that after 5 or 6 iterations, the LEDs are turning on/off about every second, then every 2 seconds, etc. After 15-20 seconds, one LED stays ON all the time, the other OFF. Following is the code I'm using :-

ENTITY LEDToggle IS

PORT

(

clk :in STD_LOGIC;

led0 :out STD_LOGIC;

led1 :out STD_LOGIC

);

END LEDToggle;

ARCHITECTURE behaviour OF LEDToggle IS

SIGNAL COUNT : INTEGER RANGE 0 TO 50000000;

BEGIN

PROCESS (clk)

BEGIN

IF clk'event and clk='1' THEN -

COUNT<=COUNT+1;

IF COUNT < 24999999 then

LED0<='1';

LED1<='0';

ELSIF COUNT>24999998 AND COUNT<49999999 THEN

LED0<='0';

LED1<='1';

ELSE

COUNT<=0;

END IF;

END IF;

END PROCESS;

END behaviour;

I'm using an EPM240T100C5 development board with a 50MHz oscillator. The LED's are on pins 2 and 8 and I'm using the clock on pin 14.

Regards

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I don't see anything wrong with your code.

I assume it must be something wrong with your clock

hi

thanks for the reply.

I was wondering about the clock also. Originally, I just set the clock pin to pin 14 in Pin Planner,then I read in an Altera MaxII guide that I should also set the clock to be a Global Signal in the Assigments Editor. I did this also, but the result was the same.

I;ve just noticed a CLK test point on the board, I'll test it with an oscilloscope.

regards

I didn't know there was a timing report - I guess I should do a lot more reading before I jump in.

I clicked on a TimeQuest link and copied parts of various reports. They mean nothing to me, but you might be able to see quickly where the problem lies.

===============================================================================================

Info: No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"

Info: Deriving Clocks

Info: create_clock -period 1.000 -name clk clk

Critical Warning: Timing requirements not met

Info: Worst-case setup slack is -12.688

Info: Slack End Point TNS Clock

Info: ========= ============= =====================

Info: -12.688 -347.450 clk

Critical Warning: QSF: Expected ENABLE_CLOCK_LATENCY to be set to 'ON', but it is set to 'OFF'

Critical Warning: In SDC, create_generated_clock auto-generates clock latency

Info: Generated Test.sdc

Info: --------------------------------------------------------

0

create_timing_netlist -model slow

check timing

no_clock 0

multiple_clock 0

pos_neg_clock_domain 0

generated_clock 0

virtual_clock 1

no_input_delay 0

no_output_delay 2

partial_input_delay 0

partial_output_delay 0

io_min_max_delay_consistency 0

reference_pin 0

generated_io_delay 0

latency_override 0

partial_multicycle 0

multicycle_consistency 0

loops 0

latches 0

pll_cross_check 0

uncertainty 1

partial_min_max_delay 0

clock_assignments_on_output_ports 0

input_delay_assigned_to_clock 0

[1] -12.688 COUNT[8] COUNT[23] clk clk 1.000 0.000 13.355

.

.

.

.

[1000] -3.811 COUNT[9] COUNT[20] clk clk 1.000 0.000 4.478

regards

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PS. forgot to mention that I have a second board with the same CPLD, which I programmed as above. The LEDs first toggled after 77 seconds (!!), then 82 then 75 seconds, then I gave up.

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you will need to set your clock frequency in an sdc file so that tool knows what to do.

create an sdc file (text file with extension sdc, go to new => files=> sdc) and type:

create_clock -period "50 MHz" [get_ports clk]

last post:

I tried again with just 1 LED, with similar results. The blink rate is about right to start with, then it increases. It seems that the LED is ON for the same amount of time, but the time for which it is OFF keeps increasing. The simplified code snippet I tried is :-

wait until (clk'event) and (clk='1');

result <= result + 1;

if result < 2500000 then

LED0<='1';

elsif result=49999990 then

result <=0;

else

LED0<='0';

end if;

hi

thanks for the reply.

I'm not sure if I've 'solved' the problem, but I tried the 1 LED programme using each of the 4 different clock pins on the EPM240T100C5 CPLD, namely p12, p14, p62 and p64 and it would only work with p12. The LED didn't even light up using the other clock pins. Do you have to use the first clock pin on the chip if you only need 1 clock ? How do you tell Quartus what the speed is, I thought you only had to do that with an FPGA, but I'm happy to be corrected.

regards

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hi

thanks for the reply.

I'm not sure if I've 'solved' the problem, but I tried the 1 LED programme using each of the 4 different clock pins on the EPM240T100C5 CPLD, namely p12, p14, p62 and p64 and it would only work with p12. The LED didn't even light up using the other clock pins. Do you have to use the first clock pin on the chip if you only need 1 clock ? How do you tell Quartus what the speed is, I thought you only had to do that with an FPGA, but I'm happy to be corrected.

regards

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I assumed you are using timequest as your post suggested and so I wrote the sdc statement for clk in one of above replies.

If timequest does not support cpld then use the classic timing analyser and enter frequency in the relevant setting.

Then quartus will tell if you passed timing or not