Least painless way to get data in & out of FPGA

Interesting. What do you mean by PC side drivers: shouldn't I just be able to open a socket on the PC and start sending, especially if the SoC takes care of getting an IP assignment?

With the PCIe core, on the FPGA side, I just get two 32-bit FIFO interfaces (read and write), literally 6 signals total. Very easy to handle.

Just spent all day working through the Qsys system design tutorial https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/tt/tt_qsys_intro.pdf There's no reference project for Cyclone V, which complicates things a bit ... but I think I almost got it working. Once I have Avalon operational, I'll try to hook it up to ethernet IP and see what happens.