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Altera_Forum's avatar
Altera_Forum
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17 years ago

Jtag Working Wrong!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

Hi everybody!

Recently,I'm debug a board about Ep2c8 which build by myself，after I welding end all devices，

I made a sample test program and download it with QuartusII8.0. Then Quartus tell me download success! But I find that fpga does't work as my test program!My test program just make fpga's some pins output as low! As a result ,all pins output as a high！

So ,Someone who know about it ,please tell me why!!

Thank you very much!

Shenhuan 2009-11-22:confused:

11 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Or who can tell me something may cause this ！

    The signalTapII does't work too!
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    What do you mean by "signalTapII does't work"? What's the status of the CONF_DONE pin?

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    SignalTap can build and download ,but when i run it ,it show me that jtag communication error!

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Did you setup the JTAG hardware correctly in Signaltap? Does it find your FPGA?

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    I meant the JTAG hardware configuration in Signaltap.

    What are the levels of the nCONFIG and CONF_DONE pins after configuration?
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    CONF_DONE should be high after the FPGA has been programmed. Do you have an external pull-up on the pin?

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    The only cause I can see is that an error occured during the FPGA configuration, but it's strange that Quartus doesn't detect it.

    There could also be a problem with one of the power supplies or a bad decoupling but I'm not sure it would prevent the COND_DONE pin from going high.

    Do you have another design that you can test?