Minh_Le
New Contributor
3 years agoJTAG to Avalon master simulation
Hi,
I want to simulate my entire design that include main_qsys IP core and Nios processor. I try to follow the link below to talk to Avalon bus via System Console in simulation; however, I couldn't download the setup_pli.tcl script. Is there anyway you can provide it? The ip cores are generated by Quartus Prime 18.1, QuestaSim version is 10.5 C . Please provide any related update if we have one since the last time it's updated was 2019.
Thanks,
-Minh
https://community.intel.com/t5/FPGA-Wiki/Avalon-ST-JTAG-Interface-PLI-Simulation-Mode/ta-p/735219