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Altera_Forum's avatar
Altera_Forum
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16 years ago

jtag signals/probes dll

Does anyone know if there is a way to access via a DLL an instantiated signals and probes megafunction? It would certainly make my life a little easier than writing my own serial io control mechanism since I can do what I need with signals and probes. I didn't know if there was an API available either to c, c++, or perhaps tcl? I would assume a DLL based interface. Just wondering if there was something out there like that rather than reinventing the wheel.

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  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Be careful saying DLL on an FPGA board, as everyone thinks Delay Locked Loop first. I thought the Signals and Probes could be accessed via a Tcl interface, but it's through a Quartus shell. I know the VJI(Virtual JTAG Interface) has a Tcl interface, as I've written scripts to access it. Of course, the VJI requires some writing of hardware too. I don't know if that's enough to do what you want. (Also, I think many designers put a small Nios in their system, use one of it's I/O interfaces to talk to a machine, and then are able to access a processor from a machine while also runnign code in the FPGA. This may be more than what you're looking for.)

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    As far as I see, the SignalTap specific Virtual JTAG protocol is undocumented. Scripting support allows an automation of the Quartus stp application, but low level access isn't discussed in the Quartus Software manual.

    Also the DLL interface, that obviously exists in the Quartus software stack, is generally undocumented, except for a particular DLL dedicated to the software UART (jtag_atlantic.dll). It has been in discussed in the forum before.

    I didn't yet feel a need to control SignalTap instances by external software, although I see a purpose. Accessing Source&Probe and In-System Memory Editor is more interesting as a general test tool, particularly for boards, that aren't equipped with a NIOS II or hardware processor. A documented interface would open this option to all Altera FPGA users. To my opinion, Altera should regard it as a cheap oportunity to improve the product versatility.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    I'm confused as you're using SignalTap and Virtual JTAG Interface, which aren't necessarily the same thing(yes, they both use the JTAG hub). I've found the User GUide useful(search on Virtual at this link, and it will have the user guide and the examples):

    http://www.altera.com/literature/lit-ug.jsp

    Also running at a shell "quartus_sh --qhelp" and looking at the available shell commands to be informing. I've gotten by running a Quartus shell and directly interacting with the VJI through Tcl, specifically device_virtual_ir_shift and device_virtual_dr_shift commands. Are you looking for something more low-level than that, so the Quartus shell is not needed? I understand that could be useful(maybe the VJI is part of the final product), but trying to understand. Not that I can make it happen or anything. (File an SR, not that that will do it, but that will show a request for enhancements...)
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Well, I've been reporting the answer of Altera support in this regard in a previous thread. I'll add the link later on. My question was about a documentation of Virtual JTAG codes, particularly the device and instance selection. Support suggested to use the tcl shell to learn the codes... In the meantime, the situation has get better, because the new Virtual JTAG user guide contains some useful information.http://www.alteraforum.com/forum/showthread.php?t=1686

    The connection of SignalTap and Virtual JTAG exists, if you intend to access the virtual JTAG instance directly without the stp application. Personally, I don't plan it yet, but it can be interesting, too.

    Virtual JTAG is a suitable interface to operate e.g. a test and calibration tool just through the standard JTAG header that is provided anyway for configuration memory programming. It would prefer this as a product feature rather than hacker knowledge.