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Altera_Forum's avatar
Altera_Forum
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15 years ago

JTAG programming with blank EPCS16

I have two PCBs, a master and slave, each with a Cyclone III FPGA on it.

The JTAG pins of the slave board are connected to IO pins on the master board. The first board has an Ethernet connection to a PC.

I have written code that enables the FPGA on the slave board to be programmed via the JTAG connections to the master board. This works fine as long as the EPCS16 on the slave board is not blank.

If I were using Altera software I would solve this problem by setting "Halt on chip configuration controller" in the Quartus programmer options. However, I'm using all my own code so how do I now set this condition?

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    You have to find out, which JTAG code is generated by Quartus for the said "Halt on chip configuration controller" action. Unfortunately, I don't know it. It may be either a generic BSDL command acting on AS interface pins or more likely a programming instruction.

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    This seems to point to the solution:

    Knowledge Base - solution id: rd12222005_990

    I've found the solution to this issue and have posted the details here

    "Complete Solution - how to JTAG program"