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Altera_Forum
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15 years ago

JTAG programming with blank EPCS16

I have two PCBs, a master and slave, each with a Cyclone III FPGA on it. The JTAG pins of the slave board are connected to IO pins on the master board. The first board has an Ethernet connecti...
Altera_Forum's avatar
Altera_Forum
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15 years ago

You have to find out, which JTAG code is generated by Quartus for the said "Halt on chip configuration controller" action. Unfortunately, I don't know it. It may be either a generic BSDL command acting on AS interface pins or more likely a programming instruction.