Forum Discussion
Altera_Forum
Honored Contributor
12 years agoI found the problem. The CONF_DONE pull-up resistor was connected to a 1.2V supply instead of 3.3V (which was the supply of the bank). Therefore, after the programming is finished, the FPGA still stays in configuration mode with 1.2V. I changed the pull-up voltage and the problem was solved. Thanks you very much for your help.