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Altera_Forum's avatar
Altera_Forum
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12 years ago

JTAG programming successful but no output on hardware

I am using a Cyclone III EP3C10F256 device. When I connect the USB Blaster and run the JTAG programmer in Quartus, the programming is done with no error. The code is just written to tie a few outputs to high or low. I have no PLLs or clocks involved yet to keep things simple. However, after the programming is done, I see no output on the pins. Everything is tied to 3.3V regardless of the configured program. I even set the default value of an input to GND, which does not show on the hardware after programming when I don't apply any input signal.

I have three voltage supplies for my FPGA: 1.2V for the core, which is okay, 2.5V for the JTAG and PLL, which are okay, and 3.3V for outputs on all banks, which look okay. I also checked the JTAG chain in Quartus which seemed okay.

I have checked to see if the FPGA returns any signal after programming by probing the TCO signal, and checked the other pins on the JTAG to make sure "something" is going to the FPGA. I also checked the pull-up and pull-down resistors on the JTAG signals and their values to make sure everything is according to the datasheet.

Can anyone help me with what could potentially be the problem?

6 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Is this a development kit, or a board you created yourself?

    Can you check the CONF_DONE output asserts high after programming? (Or the INIT_DONE optional pin, if you enable it in your configuration)

    Please review the pin assignments after the design has been synthesized, i.e., look at the pin file and look at the pin planner. Do they match your design?

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Thank you Dave.

    This is a board I've made myself.

    I checked the CONF_DONE output. During programming it goes low, and after programming it goes high.

    The pin planner looks right. Except I'm using a 3.3V supply for all the VCCIO banks and in the pin planner I see the banks which have not been used have defaults set to 2.5V and have not been changed (I don't know how to change them without associating an output pin to the bank). I tried changing the text file and setting all the VCCIO's to 3.3V manually but I'm not sure if it actually applied the changes in the next programming. I'm not sure if this could be a reason for my problem.
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Dave, I fixed the problem of different VCCIO's I mentioned in my previous post. The pin planning is perfect (pin assignments and VCCIO voltages) but the problem of not getting any outputs is not fixed. Do you have any ideas?

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    --- Quote Start ---

    This is a board I've made myself.

    --- Quote End ---

    Ok.

    --- Quote Start ---

    I checked the CONF_DONE output. During programming it goes low, and after programming it goes high.

    --- Quote End ---

    So the FPGA configured Ok. The problem must be in your code, or assignments.

    --- Quote Start ---

    The pin planner looks right. Except I'm using a 3.3V supply for all the VCCIO banks and in the pin planner I see the banks which have not been used have defaults set to 2.5V and have not been changed (I don't know how to change them without associating an output pin to the bank). I tried changing the text file and setting all the VCCIO's to 3.3V manually but I'm not sure if it actually applied the changes in the next programming. I'm not sure if this could be a reason for my problem.

    --- Quote End ---

    Nope, that will be fine. There are GUI and Tcl settings that can be used to set the default voltage.

    Email me a zip file containing your Quartus project and I'll see if I can see what is wrong (use my forum name as the email address).

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    I found the problem. The CONF_DONE pull-up resistor was connected to a 1.2V supply instead of 3.3V (which was the supply of the bank). Therefore, after the programming is finished, the FPGA still stays in configuration mode with 1.2V. I changed the pull-up voltage and the problem was solved. Thanks you very much for your help.

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    --- Quote Start ---

    Thanks you very much for your help.

    --- Quote End ---

    Thanks for posting your solution!

    Cheers,

    Dave