Stefania,
On the web there is a table that shows support for download cables. JTAG is supported for all supported cables.
http://www.altera.com/support/devices/tools/altera/cables/tls-altera-cables.html To add to what Lunatic stated in the previous post. JTAG can be used for configuration but has a few key advantages. You can scan the chain for connectivity. You can do boundary scan testing if your system and test setup supports this (Testers primarily). Altera offers BSDL files free to download. You can use SignalTap II to probe internal nodes similar to a logic analyzer for debugging. You can also use a JIC file to program EPCS devices indirectly using serial flashloader to load the flash through the connections of the download cable to the FPGA then AS to the EPCS from the FPGA.