JTAG ESD good practice

Hello,

I am trying to find in Intel / Altera documentation a statement about ESD reliability of JTAG pins in MAX 10 devices, for now with no success. Do you know something more about it? I do not have an access to IEEE 1149.1 (JTAG) standard, so I'm not sure if it is specified there.

In case of JTAG connection, I saw some designs. In most of them there is no resistor and capacitor connected - just lines from connector goes stright to FPGA. In one design I saw 22 Ohm resistor. Also I saw on this forum a thread, that in some issues related to signal integrity it is good to add small capacitor. Do you recomend to add i.e. a placeholder for pF capacitors "just in case" ?

Thanks for support.