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Altera_Forum
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15 years ago

JTAG Configuration on EP3C120F780 program loss

Hi All, i need help. I am having a problem with my board in which the configuration loss easily when handling the board. It is so sensitive that i had to re-program it everytime.

From the handbook i got the advice are

for the device vccio of 2.5, 3.0, and 3.3 v, refer to figure 9–26. all i/o inputs must maintain a maximum ac voltage of 4.1 v. because jtag pins do not have the internal pci clamping diodes to prevent voltage overshoot when using vccio of 2.5, 3.0, and 3.3 v, you must power up the vcc of the download cable with a 2.5-v supply from vcca.

Which means i need to separate out VCCA and connect it to the JTAG pins.

Does this neccesary if my VCCIO is 2.5V and i share the same power supply?

If yes, does anyone encounter program loss?

Any recommand action for troubleshooting is appreciate...

Appreciate help.........

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    With VCCIO of 2.5 V, you can use basically the same power supply for VCCA. Sufficient bypassing for all supply pins should be achieved however. You may want to provide additional filter ferrrites for PLL supply pins, but I think, it's not necessary for Cyclone III in most cases.

    --- Quote Start ---

    It is so sensitive that i had to re-program it everytime.

    --- Quote End ---

    In which situations do you observe configuration loss? Are aware of the volatile character of the SRAM configuration? You need a non-volatile memory to keep the configuration permanently. If the configuration gets lost during operation, you are possibly missing required pull-up or pull-down resistors for configuration and JTAG pins, or have an unstable power supply.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    First of all thank for replying.

    After program we will load the board to a rack manually. This is where the program loss. Sound weird. I am ruling out the unstable power supply because i have been monitoring the VCCQ for a while now.

    Do you think the VREF will affect the configuration as i am using this pin as I/O pins

    Input reference voltage for each I/O bank. If a bank uses a voltage-referenced I/O standard, then these pins are used as the voltage-referenced pins for the bank. [/I][/I]

    If voltage-referenced I/O standards are not used in the bank, the VREF pins are available as user I/O pins.[/I][/I]

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    --- Quote Start ---

    Do you think the VREF will affect the configuration as i am using this pin as I/O pins

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    It won't, very surely.

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    After program we will load the board to a rack manually.

    --- Quote End ---

    How do you "move it to a rack" without disconnecting the power supply and thus loosing the configuration?
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Yes. without disconnecting the power of course.

    How about nCONFIG pins. Do you think that it make any difference if i connect it to high as recommanded by Altera spec. Currently it is floating