Hi The last week I wrote a post about a problem with the configuration of the EP3C5E144C8N cycloneIII FPGA: ------------- I´m trying to program a EP3C5E144C8N FPGA in JTAG mode using a ByteBlasterII cable. The pins are connected as indicated in the JTAG configuration of a single device using a download cable (Fig 10.24 of the Cyclone III handbook). All the power suplies used have been measured in the device and are OK. When I test the JTAG chain integrity the QuartusII return the messages: -No device detected -The TDO connection to the dowload cable migth be shorted to VCC or is an open circuit -The TCK and TMS connections to the last device migth have problem. --------------- After that ,I have done a lot of test and unfortunately I can´t solve the problem. I check the signals TDI, TMS and TCK and they are OK (signals transitions when I press Start in the IDCODE iteration test) but I dont´t have nothing in TDO, just 1V of DC (not the expected transitions). All the power voltages are OK in the respective pins. The exposed pad is connected to ground I´m using 2.5V as power supply of the ByteBlasterII cable. I have change the device and I have been very carefully with the ESD but nothing, the same error. I´m considering some error in my electric design, I attached a file with the design, maybe you can help me to find the error. Thanks a lot

Sorry, Here is the attached circuit

A few questions L1 - L3 are these inductors or ferrit beads ? As MEL0 .. 2 are 0, you have selected passive serial as configuration mode but why do you keep pin 14 nConfig = VCCIO ??? you will never be able to use this configuration mode, only JTAG why do you force UDCLK pin 12 to DGND ? JTAG Header CN2 seems to be correct, but i would recommend to connect PIN 6 to VIO as well, you never know what blaster you will use in the future what type of LDO do you use as U4 for the 1,2V ??? is it a fast transient response type ? are there is only one caps 4,7uF for each voltage source ? i believe that is too smal. have you calculated the max. voltage ripple with these few micro farads and compared it with the device datasheet ? what is you external clock at clk3 ?

If 4.7u || 100 pF on each power node is all your bypassing, you may experience problems in device operation. I would suggest additional 100n near each supply pin. But the JTAG chain should be accessible. I also stumbled upon nCONFIG tied to VCC. But Altera says, connect it to logic high with JTAG only configuration, the same with DCLK/DATA0 connected to ground. So I don't see an obvious error in the schematic. Personally I think, providing an optional AS flash would be a good idea. There's always a possibility, that ByteBlaster is defective. If you can't verify it's operation with a different board, you should check, that all JTAG signals are arriving at the FPGA pins with correct level. According to the Cyclone III device handbook, irregular power supply sequencing can be an issue, e.g. no valid VCCIO present when VCCINT and VCCA, that control the POR circuit, have reached nominal levels. But I don't think that this is likely to cause problems in your case.

Hi MSchmitt and Frank Thank you for your answers. In this application I will use only JTAG, that´s why I connected MSEL 0,1,2 to ground. Is not correct? I checked with an oscilloscope the JTAG signals arriving to the corresponding pins and they are OK (TDI, TMS and TCK). TCK is normally in 0V and when I press the start button appear a pulse burst with 2.5V of amplitud. The same with TDI and TMS but they are normally in high level and the pulse bursts are inverted. The output signal TDO is normally around 1V but it doesn´t change, is that normal? If the ByteblasterII is sending TDI, TMS and TCK signals, could it be damaged? L1-L3 are ferrite beads 0603 case. U4 is a High Speed LDO Regulator (XC6214 Series). I used a 10MHz external clock in my circuit (clk3), but I have not connected it yet, I will use it once programmed the FPGA as timing sequence. Thanks for the advice in use a 100nF near each supply pin, I will put in the board. I Hope you can help me, thanks again

Unfortunately, your post doesn't bring an approach to explain the issue, everything seems right so far. MSEL = "000" is suggested in the device handbook for JTAG only configuration, but I didn't ever use it. Seeing correct logic levels from all JTAG signals should ususally be sufficient to validate the ByteBlaster operation. Finally there is a risk, that the FPGA has been damaged during assembly or my massive overvoltages. Personally, I would rather expect some kind of non-obvious wiring error or missing supply connection. I fear, there's no chance to further assist you from a distance.

JTAG configuration error in CycloneIII | Altera Community

20 Replies

Altera_Forum
Honored Contributor
16 years ago
the jtag part of the device uses the voltages you provide with your design.
for example if your gnd level gets shifted due to undervoltages then part of or the complete device may fail.

i would go for 4 layer pcb minimum.
top layer
vccio PLANE !
gnd PLANE !
bottom layer with vint and vca and some tracks

remember to draw the power supply first make the tracks as short and wide as possible
try to avoid that you combine tracks that go to one via somewhere on you pcb. instead go as soon as possible into your internal layer. the internal layer must be planes and not tracks. so you have the possability to place bigger caps and more caps with short tracks and more than one via to these layers what helps you to control your voltages.

those tracks from your LDO to the destination pins were too smal and too long.
place the LDO closer to the fpga.

these are only a few basics
Altera_Forum
Honored Contributor
16 years ago
--- Quote Start ---
for me it is clear that you have these problems
--- Quote End ---

I don't think, it's that simple. I have designed a number of two layer PCB FPGA boards with ACEX1K, Cyclone and Cyclone II, mostly prototypes, but also a small production board, that's manufactured since five years, and I had never problems of the said kind. Also forum members have presented surprizingly simple boards, that have been finally working. The present board has possibly more problems due to additional flaws, e.g. missing supply bypassing and a too light ground net. I would expect JTAG to respond though, at worst showing errors with large bit streams, but still able to give a chip ID.

To avoid misunderstandings. I don't generally suggest to design two layer PCB with FPGA. I also see 4 layer as a minimum for PQFP/TQFP packages and 6 layers minimum for full populated BGA. And I know, that a design can fail due to a bad layout. But I don't see it as a plausible explanation for the configuration problems. If signal quality issues are actually causing the configuration problems, you would be able to measure it.

P.S.: How did you solder the FPGA?
Altera_Forum
Honored Contributor
16 years ago
Hi Frank

I´ve been confused about the layout design as a probable cause to the errors in the configuration load with JTAG.
I soldered the FPGA manually, thats is my best candidate in the errors that I have found. I have been very carrefully with the handling of the device and some people said me that they are not very sensitives. The worst part was the soldering of the exposed pad because I had to heat a bit the pad to guarantee the rigth connection.
Thanks
Altera_Forum
Honored Contributor
16 years ago
--- Quote Start ---
some people said me that they are not very sensitives
--- Quote End ---

Thin packages are generally sensitive against delamination (cracking of the package due to evaporation of absorbed water during solder process), particularly if you don't keep the handling rules. It's e.g. necessary to perform a baking procedure when assembling the part after the floor lifetime of one week has expired. I think there's also a risk of overheating the device with small hot air tools. In my opinion, the best method to solder the exposed pad (together will all other pins) is a hot plate, a reflow oven, or a professional hot air tool with sufficient large nozzle. I agree, that with a suitable treatment, the parts aren't very sensitive.
Altera_Forum
Honored Contributor
16 years ago
Hi MSchmitt and Frank

Finally I found the error origin. As I suspected the configuration load failed because the soldering of the cycloneIII. As a last desperate resource I push down the component against the board and try to program and.. surprise!! it works..
I resolder again the component and now is fine. The surprissing part is that before of that, I checked pin to pin the continuity connection (without apply a big force) and it seemed OK, but not.
Well, I´m more tranquil now. Thanks for your answers, I will use all your advices in the final design of my board
Best regards
Altera_Forum
Honored Contributor
16 years ago
That's good news !
If you have any questions feel free to ask again.
Enjoy your design and have a lot of fun with it.
Altera_Forum
Honored Contributor
16 years ago
Very good. I'm not surprized, however.
Altera_Forum
Honored Contributor
14 years ago
Please help me for my design,

I am using your same device. I am trying to configure the this chip using Terasic blaster. But error came while the configuration. is it support with blaster and any special setting for this device.please give your model design.
Altera_Forum
Honored Contributor
14 years ago
Please help me for my design,

I made a prototype using your same device[EP3C5E144C8N]. I designed the circuit in JTAG configuration only. But I am using the Terasic USB Blaster download cable and Byte Blaster MV. In this case no response from the target board. My design has as per the Altera documents.

But Terasic documents said that, It is only for Cyclone I and cyclone II family of devices in the altera cyclone series. I have doubt in the JTAG voltage levels, they are VCCIO and VCCA.

Is it more difference between cyclone II and cyclone III. But I have successfully programmed the cyclone II family device using USB Blaster and as well as Byte Blaster..,

can I set 3.3v for the VCCA line. But mostly preferred this level is 2.5 V.
I have more confusion in this area.

do I change the download cable design for that?
If it changes that please tell me?
Can I give same voltage rating for VCCIO and VCCA?
The 6th pin on JTAG connector is VCCIO but the blaster line is tell it for nCE? what I do?

please show me your design in that particular area?

Is it possible to program the cyclone III family device in normal download cable(Terasic USB Blaster or Byte blasterMV)
Altera_Forum
Honored Contributor
14 years ago
No the VCCA needs to be at 2.5V. If you connect it to 3.3V you'll probably damage the Cyclone III.
VCCIO is supposed to be on pin 4 of the JTAG connector, not pin 6. Pin 6 isn't used by the blaster in JTAG mode anyway, so I don't think it matters a lot.
I see you are using the E144 package. Did you remember to connect the exposed pad on the bottom of the chip to ground? If you don't do it the component won't work and you won't be able to configure it.

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JTAG configuration error in CycloneIII

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