Forum Discussion
Altera_Forum
Honored Contributor
16 years agoHi Frank
I´ve been confused about the layout design as a probable cause to the errors in the configuration load with JTAG. I soldered the FPGA manually, thats is my best candidate in the errors that I have found. I have been very carrefully with the handling of the device and some people said me that they are not very sensitives. The worst part was the soldering of the exposed pad because I had to heat a bit the pad to guarantee the rigth connection. Thanks