Serge93
Occasional Contributor
Occasional ContributorJTAG Chain Broken on Agilex 7-I Dev Kit
Hello Support, Today suddently, I could not configure anymore my Agilex 7-I Dev Kit. I got the following message :
Forum Discussion
FakhrulA_altera
Regular Contributor
Regular ContributorHi Serge93,
Thanks for reporting this. Please try these quick steps:
- On the host, restart the JTAG server and run jtagconfig, or use the JTAG Chain Debugger to isolate the issue. Refer: JTAG error (Unexpected error in JTAG server
- Return the board to factory default switch settings and select the on‑board Download Cable as the JTAG source. Refer: Factory Default Switch Settings
- Temporarily bypass the FPGA in the JTAG chain (SW5.2 or SW8.2 by board revision), then attempt a Board Restore to recover the MAX 10 and factory image. Refer: JTAG chain broken after FPGA configuration
- If it still fails, try an external USB‑Blaster II and reduce the JTAG clock in Programmer.
Please share your kit ordering code and the output of jtagconfig --debug after step 3.
Regards,
Fakhrul
Serge93Occasional Contributor
Occasional ContributorHello Fakhul,
I already did all what you said including trying to access the board through the BTS. I was able to reconfigure the MAX10 by bypassing the FPGA but it changed nothing. The Agilex 7i is impossible to configure even with an external USB Blaster with reduced clock.
kit ordering code : AGIPCIe8100650 / N24193-001
The Result of jtagconfig --debug is :
[niosv-shell] C:\Users\serge\AppData\Local\quartus> jtagconfig --debug
1) AGI FPGA Development Kit [USB-1]
(JTAG Server Version 25.3.1 Build 100 12/19/2025 SC Pro Edition)
Unable to read device chain - JTAG chain broken
Captured DR after reset = ()
Captured IR after reset = ()
Captured Bypass after reset = ()
Captured Bypass chain = ()
JTAG clock speed auto-adjustment is enabled. To disable, set JtagClockAutoAdjust parameter to 0
JTAG clock speed 24 MHz
Thanks for help.
Serge
- FakhrulA_altera
Hi Serge,
Thanks for the update. Could you try below:- Return all switches to Default Settings. Include: SW2[1:3] = OFF/OFF/OFF (JTAG mode), SW5.1 = OFF (on‑board Download Cable), SW5.2 = OFF (FPGA in chain), SW5.3 = ON (MAX 10 JTAG enabled). If your board uses SW8 instead of SW5, use the equivalent entries in the same table. Refer: Default Settings tables.
- Check the D6 Power Good LED. Blue ON means all rails are good. If OFF, address power first. Refer: LEDs table.
- In BTS, open Power Monitor GUI and capture the rail status screenshot. Refer: “Monitor On‑board Power through Power Monitor GUI.”
- In Quartus Programmer, run JTAG Chain Debugger and share the integrity report if auto‑detect still fails. Intel help recommends this when the chain cannot be scanned.
- Perform Board Restore through Quartus Prime Programmer, then power cycle and retry JTAG. Refer: “Perform Board Restore through Quartus Prime Programmer.”
You may refer to this user guide for the above steps: Agilex™ 7 FPGA I-Series Development Kit User Guide
If the chain is still broken with the FPGA in the path after the above, it suggests a board‑side JTAG issue, it can indicate a board integrity problem once power and connections are confirmed. We can proceed with RMA.
Please also share clear photos or a list of the current SW1–SW6/SW8 positions.
Regards,
Fakhrul- Serge93
Hello Fakhul,
So,
About (1) : I have set all the switches as asked, please see the picture attached.
About (2) : Unfortunately The LED D6 is Off.
About (3) : See the picture attached, I cannot communicate with the board, So I cannot get any voltage value.
About (4) : Please see the attached picture.
About (5): I had to use the J10 instead of J8 to be able to reconfigure the MAX10, otherwise I cannot get the JTAG chain and so I cannot configure the MAX10. I power cycle and the JTAG is still the same...
Thank you for your help.
Serge
