New ContributorJTAG chain broken after FPGA configuration
Hi there,
I am using an Agilex 7 I-series Development Kit (DK-DEV-AGI027R1BES, AGIB027R29A1E2VR3), and Quartus 24.1 on Linux.
After programming the device with a CXL Type 3 Example Design and restarting the server, the FPGA's JTAG chain is no longer operational. When I run `jtagconfig --debug`, I see:
```
1) AGI FPGA Development Kit [1-1]
(JTAG Server Version 24.1.0 Build 115 03/21/2024 SC Pro Edition)
Unable to read device chain - JTAG chain broken
Captured DR after reset = ()
Captured IR after reset = ()
Captured Bypass after reset = ()
Captured Bypass chain = ()
JTAG clock speed auto-adjustment is enabled. To disable, set JtagClockAutoAdjust parameter to 0
JTAG clock speed 24 MHz
```
I used `quartus_pgm` to program the FPGA (configuration file passed via `-c`, copied below). This should use the on-board USB blaster, as opposed to an external blaster. These steps worked well in an internal project built on top of the Type 3 example design. However, when I used this config on a newly generated Type 3 example design project and ran it, the JTAG issue occurred.
```
```
Thanks in advance for your help.
We were able to restore the JTAG chain by switching SW8.2, which disables the FPGA on the JTAG chain. Once we do that, we were able to restore the max10 device using the factory recovery steps as described in the files that came with the board.
