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Altera_Forum
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15 years ago

JTAG can’t find device

Hi all,

I am a beginner of Altera's device.

Today, When I use the JTAG mode of Quartus’ programmer to configure the device EP3C5E144, the programmer always says “Unable to scan device chain. Can’t scan JTAG chain.”

When the programmer tried to scan the chain, I test the TDI, TDO, and TCK. There is data wave on TCK and TDI, but the TDO never changed and always hold about 2.2V.

All the power, 1.2V, 2.5V, 3.3V, is OK. I used 2.5V to power the JTAG connector, and added a 1k resistor between 2.5V and 3.3V (pin 6).

Besides, NCE holds 0V. Though I have pulled up the signals, Config_done and nstatus, they all keep 0.033V.

I also use a flash to configure the FPGA in AS mode. The programmer can download code to flash successfully, however the FPGA shows no action no matter I re-power up the system or not, and there is no clock on DCLK.

The Usb blaster should be right, because I can configure some other boards. Could anybody give me some suggestion?

18 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Yes, the normally value of TMS is 3.3V and during the scan period, there will be some low level signals.

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Well if your usb blaster is ok, all the connections are right and there's activity on all JTAG input signals, probably your device is broken.

    Any chance you could post the schematics of your design?

    -- Ton
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Thank you Ton.

    I have soldered two boards. And they all show the same phenomenon. I don't think the FPGA is broken also because the config_done and Nstatus are nearly 0.

    However, I don't know where is the problem. I have attached the schematic and I hope some people could tell me why.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Did you connect the FPGA's exposed pad to ground? Your schematic doesn't seem to mention it.

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    --- Quote Start ---

    Thank you Ton.

    I have attached the schematic and I hope some people could tell me why.

    --- Quote End ---

    The schematic looks ok to me. How about Daixiwen's remark? The exposed pad should definitely be connected to GND.

    Succes, Ton
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Hi Ton and Daixiwen,

    I treated this expose pad for heat emission and placed a big pad under it. However, I don't connect the expose pad to GND. Is this very important? Anyway, I will have a try.

    Would you please help me to think about whether there is other possible issue?Thank you very much.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Yes, it is important. See page 1-4, note 7 of the CIII Handbook.

    It's just a small note in a big handbook, but important.

    Success, Ton
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    You should try that first Bad exposed pad connections are well known to cause problems with JTAG communications.

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    When I connect the pad to GND, I can configure the FPGA in JTAG. In the programmer, I select the JTAG mode and click auto detect, the software can find a device EP3C10, not EP3C5E144. However, if I just add the “.sof” file directly, then the code can be download successfully and FPGA perform a right action.

    Thank you, Ton and Daixiwen.