New Contributor
Regular ContributorHi,
Please refer to the user guide under section 3.1 Development Board Setup
Please ensure that all switch is on the default setting as per mention in the user guide.
Regards,
Wincent_Intel
New ContributorI don't have a development board. This design targets our own custom hardware.
Regular ContributorHi,
Can you see any burn marks on your custom hardware ?
or there is any connection fail on the power cable ?
Regards,
Wincent_Intel
New ContributorHello.
There is nothing wrong with the board. Let me summarize again:
1. We have two FPGA designs that target the exact same board design.
2. FPGA design A supports 4 lanes of video which each run at 5Gbps. This design uses the PCIe Gen 2 x 8 core.
3. FPGA design B supports 4 lanes of video which each run at 10Gbps. This design uses the PCIe Gen 3 x 8 core.
4. The same physical board was used for all testing.
5. The PCIe Gen 2 x 8 build fails in various ways detailed earlier in this thread. I have done multiple DSE runs and all have a success rate of 30 - 40%, meaning some results work as expected. 13 out of 33 builds work.
6. The PCIe Gen 3 x 8 build always works 100%. I have done two seed sweeps of 10 and including base that means 22 builds work fine.
7. When I perform a seed sweep on the Gen 2 x 8 design using Quartus 17.1 all results work fine. 11 out of 11 work.
We need to understand what breaks the Gen 2 x 8 design in Quartus 22.3.
Thanks,
Mike
