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ALTERA-INSUPPORT22
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2 years ago

Issue with Multi-Core Firmware Execution on Intel Cyclone V SoC

I am working on intel cyclone V SoC I have two cores in a processor Core 0 core 1, I want two firmware to run on two different cores core 0 and core 1 in bare metal .


In linker/scat file core 0 entry point is 0x60000 and linker/scat file core 1 entry point is 0x100000

Right now when I build project and as a result two separate bin files are generated which then placed in qspi

quartus_hps -c 1 -o P -a 0x0060000 core0.bin

quartus_hps -c 1 -o P -a 0x00100000 core1.bin

But the problem is core 0 works fine but core 1 not working apart form that I am taking care in the code of core 0 about setting cpu1startaddress 0x100000 and also taking core 1 out of reset


Is there any way to combine the two bin into 1 or any lead/suggestion to solve this issue

Regards

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