Forum Discussion
New ContributorIssue with Multi-Core Firmware Execution on Intel Cyclone V SoC
I am working on intel cyclone V SoC I have two cores in a processor Core 0 core 1, I want two firmware to run on two different cores core 0 and core 1 in bare metal .
In linker/scat file core 0 entry point is 0x60000 and linker/scat file core 1 entry point is 0x100000
Right now when I build project and as a result two separate bin files are generated which then placed in qspi
quartus_hps -c 1 -o P -a 0x0060000 core0.bin
quartus_hps -c 1 -o P -a 0x00100000 core1.bin
But the problem is core 0 works fine but core 1 not working apart form that I am taking care in the code of core 0 about setting cpu1startaddress 0x100000 and also taking core 1 out of reset
Is there any way to combine the two bin into 1 or any lead/suggestion to solve this issue
Regards
3 Replies
ALTERA-INSUPPORT22@ anyone?
- ALTERA-INSUPPORT22
?
tehjingy_AlteraRegular Contributor
Hi
There is a a duplicate case created by you in the link below:
I will proceed to close this case and we will follow up with the issue in the link above.
Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.
If you happened to close this thread you might receive a survey. If you think you would rank your support experience less than 4 out of 10, please allow me to correct it before closing or if the problem can’t be corrected, please let me know the cause so that I may improve your future service experience.
Regards
Jingyang, Teh
