Is there some relationship between Current Strength and pll-locked?

--- Quote Start ---

Is there some relationship with Current Strength and pll-locked?

--- Quote End ---

Unfortunately yes. The reason is most likely simultaneous switching noise (SSO). Operating the SDRAM interface at higher output current causes interfering signals, mainly at the GND pins ("ground bounce"), that can disturb PLL operation. Either via the PLL input clock or VCCA and GNDA PLL power supply. The problem is particularly present with "huge" PQFP packages and respective long GND pathes in the package lead frame.

Some means that can improve the situation(except reducing current strength):

- differential PLL INCLK

- better bypassing and filtering of PLL supply

- improving FPGA GND connection

- utilizing unused I/O pins as additional GND connection ("output driving GND")

The means are not necessarily succesful in all situations. The good news is, that Cyclone III has considerably reduced PLL lock problems by adding an on-chip VCCA voltage regulator.

You should be aware, that even temporary PLL loose of lock implies, that all specified phase relations between PLL input and output clocks could be lost. Also erratic behaviour of the design logic must be feared.

@ FvM

very well substantiated state of knowledge as always.

@cxybuaa

in addition to that what FvM said, setting the current strength to a correct value minimizes the overshots and undershots of your signal. undershots for example can shift the input low level and lead to false triggered registers. to find the best current stregnth value means to monitor the signal shape between over/undeshots (current too high) and the slew rate to slow (current too low)..

We measured a couple of different Cyclone II boards we did here and 12mA was for all these boards the best value between the FPGA and the external SDRam, but that might be different depending on the used components and the board itself.