Is there some relationship between Current Strength and pll-locked?

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Is there some relationship with Current Strength and pll-locked?

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Unfortunately yes. The reason is most likely simultaneous switching noise (SSO). Operating the SDRAM interface at higher output current causes interfering signals, mainly at the GND pins ("ground bounce"), that can disturb PLL operation. Either via the PLL input clock or VCCA and GNDA PLL power supply. The problem is particularly present with "huge" PQFP packages and respective long GND pathes in the package lead frame.

Some means that can improve the situation(except reducing current strength):

- differential PLL INCLK

- better bypassing and filtering of PLL supply

- improving FPGA GND connection

- utilizing unused I/O pins as additional GND connection ("output driving GND")

The means are not necessarily succesful in all situations. The good news is, that Cyclone III has considerably reduced PLL lock problems by adding an on-chip VCCA voltage regulator.

You should be aware, that even temporary PLL loose of lock implies, that all specified phase relations between PLL input and output clocks could be lost. Also erratic behaviour of the design logic must be feared.