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Altera_Forum
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16 years ago

Is there some relationship between Current Strength and pll-locked?

Hi, My design implements a PLL and a SDRAM controller, but not only. I can view PLL's locked signal by SignalTap. By default, the current strength of signals from FPGA(EP1C6Q240C8) to SDRAM is 24...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

@ FvM

very well substantiated state of knowledge as always.

@cxybuaa

in addition to that what FvM said, setting the current strength to a correct value minimizes the overshots and undershots of your signal. undershots for example can shift the input low level and lead to false triggered registers. to find the best current stregnth value means to monitor the signal shape between over/undeshots (current too high) and the slew rate to slow (current too low)..

We measured a couple of different Cyclone II boards we did here and 12mA was for all these boards the best value between the FPGA and the external SDRam, but that might be different depending on the used components and the board itself.