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Altera_Forum
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12 years ago

Is my Cyclone 2 in self protection mode ?

Hi all I have a relatively simple application running on a Cyclone 2 EP2c8, where the FPGA is the master for high speed bidirectional communication signals to another module. During operatio...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

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Thanks for the clarification. I think you are correct that it is probably due to a timing issue with the FPGA ending up in a undefined state. Cheers.

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Verified the issue is due to a synchronization issue between a signal at a pin (asynchronous) and internally clocked signal. Adding a synchronous delay to pin signal before the logic operation removed the need for reset.

Thanks,

Adrian