Forum Discussion
12 Replies
- AnandRaj_S_Intel
Regular Contributor
Hi Kermit,
Yes, files will be encrypted.
Regarding error
You must compile Altera simulation model files before simulating an Altera design.
You can use any of the following methods to compile Altera simulation models.
To compile all required libraries at once with EDA Simulation Library Compiler, follow these steps:
- On the Tools menu, click Launch EDA simulation library compiler.
- Under EDA simulation tool, in the Tool name box, select a simulation tool. The Executable location box displays the location of the simulation tool you specified. You must set this location before you can run the EDA Simulation Library Compiler.
- Under Library families, select one or more family names and move them to the Selected families list.
- Under Library language, select VHDL, Verilog, or both.
- In the Output directory field, specify a location in which to store the compiled libraries.
- Click Start Compilation.
Let me know if this has helped resolve the issue you are facing or if you need any further assistance.
Regards
Anand
- KLohr
Occasional Contributor
Anand,
Thanks for getting back to me. I am using Quartus Prime Lite edition 18.1 with the Modelsim-Altera (free) simulator and I am not allowed to Launch EDA simulation Library compiler. I get the following message:
I have created a test fpga that shows the problem I am having. To keep the size smaller, you will have to
1. Unzip the file testfpga.zip to your c drive .
2. Use quartus prime lite 18.1 to open the project testfpga.qpf
3. Compile the project
4. Simulate with Tools/Run Simulation Tool/RTL Simulation and you should see the problem.
5. I am able to compile the individual IP OK, but vsim has the problem not being able to access fiftyfivenm_ver, etc
- AnandRaj_S_Intel
Regular Contributor
Hi,
I have followed steps. can't see any error.
Attached transcript & image.
If you still facing problem manually launch modelsim and load msim_setup.tcl.
Regards
Anand
- KLohr
Occasional Contributor
Yes, but are you using Modelsim-Altera (free) simulator? Kermit
- AnandRaj_S_Intel
Regular Contributor
Yes, You can check that in transcript.
modelsim_ase(Altera Starter Edition).
- AnandRaj_S_Intel
Regular Contributor
Okay,
Please read msim_setup.tcl file. Your design testfpga is having two IP we have to use both msim_setup.tcl and create a simple script like below and use.
in msim_setup.tcl add under Elaborate session add => -L dual_boot_0 -L onchip_flash_0
Commands which i ran in modelsim
source C:/Users/anandr1x/Downloads/testfpga/dual_cfg_ip/simulation/mentor/msim_setup.tcl
source C:/Users/anandr1x/Downloads/testfpga/flash_ip/simulation/mentor/msim_setup.tcl
vlog C:/Users/anandr1x/Downloads/testfpga/testbench.v
vlog C:/Users/anandr1x/Downloads/testfpga/testfpga.v
set TOP_LEVEL_NAME testbench
com
elab
Regards
Anand
- KLohr
Occasional Contributor
Please send me your msim_setup.tcl file. My testrun.do already has the -L dual_boot_0 and -L onchip_flash_0 in the vsim command. But they are not found I don't understand why this is so complicated. Why isn't my modelsim-Altera edition working like yours? Why did I have to explicitly instantiate the fiftyfivenm_ver lib? This is very frustrating. Kermit- AnandRaj_S_Intel
Regular Contributor
Hi,
steps & Compiling library is important.
PFA.
Now you extract the file and use the commands from above post copy and past and hit enter.Do change source to appropriate directory.
Regards
Anand
- KLohr
Occasional Contributor
Thanks for your patience Anand. I unzipped the file and ran the commands exactly as you have indicated with the same result: "# ** Error: (vsim-3033) c:/testfpga/flash_ip/synthesis/submodules/altera_onchip_flash.v(309): Instantiation of 'altera_onchip_flash_block' failed. The design unit was not found.# Time: 0 ps Iteration: 0 Instance: /testbench/testfpga/flash_ip/onchip_flash_0 File: c:/testfpga/flash_ip/synthesis/submodules/altera_onchip_flash.v"
It also couldn't find dual_cfg_ip. The transcript is attached.
- AnandRaj_S_Intel
Regular Contributor
Kindly redo the project and check.