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Altera_Forum
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15 years ago

is it possible internal signal to be in process sensitiv list (vhdl)

hello i am using ciclone 2. i do vhdl module and i want to ask is it possible itnernal signal to be part of sensitive list of process: process (clock, second, ten_7segment_sign_vector ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Yes, but what you are doing is very bad. Use the clock as a clock ONLY. dont make your own clocks unless they are the output of a PLL.

Generate enable signals instead.