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Altera_Forum
Honored Contributor
Honored Contributoris it possible internal signal to be in process sensitiv list (vhdl)
hello i am using ciclone 2. i do vhdl module and i want to ask is it possible itnernal signal to be part of sensitive list of process:
process (clock, second, ten_7segment_sign_vector ...
Altera_ForumHonored Contributor
Honored ContributorYes, but what you are doing is very bad. Use the clock as a clock ONLY. dont make your own clocks unless they are the output of a PLL.
Generate enable signals instead.
