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If that is the case, then it removes the majority of the usefulness of source synchronous mode. I would expect that mode to instruct the fitter to keep the data/clk phase of the internal, zero phase shifted PLL output to be the same. That allows the phase shift parameter to control how far the sample clock edge is into the data window. If the fitter keeps the data/clk phase the same using the the phase shifted output, then there is no way to adjust the sampling edge for an edge-aligned, source sync input. This is counter to the information in AN-433 "Constraining and Analyzing Source Synchronous Interfaces" and "Source Synchronous Timing with TimeQuest" - by Ryan Scoville.
If the PLL is in normal mode, then there is no compensation to compensate for the data/clk path skew. It now has to be done manually by adjusting the PLL phase and any IDELAY blocks in the data path.
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Well I can't speak for Altera PLL modes. But following definitions of source synchronous modes it becomes a guess what is exactly the effect of PLL non-zero phase in this mode.
I read several definitions of this mode, some weird but this one makes sense, just :
"Source-Synchronous mode—maintains the same phase relationshipfor data and clocks that arrive at the same time at the clock and dataports of any I/0 element (IOE) input register"
I think the best thing is to experiment it.
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