Altera_ForumHonored Contributor14 years agoIOE Programmable delay for ArriaGX issueHi dears: How to implement output register to output pin delay on ArriaGX? There should be 2 available settings and max offset 0.717ns for ArriaGX devices, but how can i realize it? Thanks in advance!
Recent DiscussionsNetlength Agilex5 028BAgilex 7 Decoupling capacitor scaling factorArria 10: Remote Update Factory Fallback won't work & Watchdog does not triggerMax10 FPGA Programming with .pof fileAgilex 5 RSU, application image addition failsSolved